Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B820F2048GL192 /QSPI0 /IRQSTATUS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IRQSTATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MODEMFAIL)MODEMFAIL 0 (UNDERFLOWDET)UNDERFLOWDET 0 (INDIRECTOPDONE)INDIRECTOPDONE 0 (INDIRECTREADREJECT)INDIRECTREADREJECT 0 (PROTWRATTEMPT)PROTWRATTEMPT 0 (ILLEGALACCESSDET)ILLEGALACCESSDET 0 (INDIRECTXFERLEVELBREACH)INDIRECTXFERLEVELBREACH 0 (RECVOVERFLOW)RECVOVERFLOW 0 (TXFIFONOTFULL)TXFIFONOTFULL 0 (TXFIFOFULL)TXFIFOFULL 0 (RXFIFONOTEMPTY)RXFIFONOTEMPTY 0 (RXFIFOFULL)RXFIFOFULL 0 (INDRDSRAMFULL)INDRDSRAMFULL 0 (POLLEXPINT)POLLEXPINT 0 (STIGREQINT)STIGREQINT 0 (RXCRCDATAERR)RXCRCDATAERR 0 (RXCRCDATAVAL)RXCRCDATAVAL 0 (TXCRCCHUNKBRK)TXCRCCHUNKBRK

Description

Interrupt Status Register

Fields

MODEMFAIL

Mode M Failure

UNDERFLOWDET

Underflow Detected

INDIRECTOPDONE

Indirect Operation Complete

INDIRECTREADREJECT

Indirect Operation Was Requested but Could Not Be Accepted

PROTWRATTEMPT

Write to Protected Area Was Attempted and Rejected

ILLEGALACCESSDET

Illegal Memory Access Has Been Detected

INDIRECTXFERLEVELBREACH

Indirect Transfer Watermark Level Breached

RECVOVERFLOW

Receive Overflow

TXFIFONOTFULL

Small TX FIFO Not Full

TXFIFOFULL

Small TX FIFO Full

RXFIFONOTEMPTY

Small RX FIFO Not Empty

RXFIFOFULL

Small RX FIFO Full

INDRDSRAMFULL

Indirect Read Partition Overflow

POLLEXPINT

The Maximum Number of Programmed Polls Cycles is Expired

STIGREQINT

The Controller is Ready for Getting Another STIG Request

RXCRCDATAERR

RX CRC Data Error

RXCRCDATAVAL

RX CRC Data Valid

TXCRCCHUNKBRK

TX CRC Chunk Was Broken

Links

() ()